The present invention generally relates to an error processing technique for use in an information or data processing system. More particularly, the invention concerns an error processing method and an apparatus which are advantageously suited for remedying fixed errors taking place in an instruction storage of an information processing system.
As methods of remedying a fixed error occurring in the instruction storage or memory in which a storage bit is destroyed in the state corresponding to a particular value "0" or "1", there have been heretofore known the following methods.
According to a first method, a value inverting bit is included in an instruction word for inverting the contents of the instruction word upon occurrence of a fixed error with the inverting bit set to "1". Upon decoding, the content of the instruction word is inverted again when the value inverting bit is "1" (reference may be made to, for example, JP-A-50-23951).
According to a second known method, when the fixed error is correctable, information for correcting the bit suffering the error is stored in an alternative storage, wherein the error bit is replaced by the correcting information upon execution of the error suffering instruction word (reference may be made to, for example, JP-A-56-22143).
According to a third known method, there are provided a plurality of error address registers and an error data register, wherein upon occurrence of uncorrectable fixed error, the address of the erroneous word and the corrected data are stored in the aforementioned registers. Upon execution of an instruction at the address of the erroneous word, the corrected information stored in the error data register is made available in place of the erroneous instruction word (reference may be made to, for example, JP-A-59-90149).
The first mentioned method is however disadvantageous in that the inverted word itself often suffers error again when error of the same value or nature covering at least two or more bits (i.e. error in which all the error bits assume the same value "1" or "0") is present in the instruction word. More specifically, assume that a correct data word consists of the two bits "01". When both bits are destroyed in the sense that they take the same value "0" or alternatively "1" (i.e. "00" or "11"), the word resulting from the inversion which should correctly be "01" again suffers error (i.e. "11" or "00"). Further, because of the need for one bit to serve as the value inverting bit, the memory utilization efficiency is correspondingly degraded which represents another disadvantage. The second mentioned method also has a drawback in that the hardware resource as required is of increased complexity because of the necessity of providing separately the alternative storage in addition to the instruction storage. Further, the objectives to be remedied are restricted to those errors which can be corrected by the error correcting circuit. When this method is intended to be applied to an uncorrectable error, such error which covers plural bits will also have to be dealt with. In that case, information of locations of plural bit data for the correction must be available, which means that the hardware resource as required is undesirably increased in complexity. The third known method requires a plurality of error address registers and error data register, as mentioned above, wherein the address of every instruction to be executed must be compared with the contents of the error address register without fail. As a consequence, the cost of the hardware resource required for the control of this end is increased, which also represents a disadvantage.